Mixer Topology Selection for a Multi-Standard High Image-Reject Front-End

In this paper, a mixer topology selection for a multi-standard high image-reject front-end is presented. The receiver is intended to work for Digital Enhanced Cordless Telephone (DECT) systems (at 1.9 GHz and 2.4 GHz) and for Bluetooth (at 2.4 GHz). It will be implemented in 0 18 μm CMOS technology. A double-quadrature low-IF architecture is employed because it can provide a high image rejection and flexibility for different standards. Building block specifications are optimized in order to achieve high image rejection and high sensitivity. Since the downconverter is the core of the front-end, it is necessary to select a high performance mixer topology that can provide low noise figure, high voltage gain, low power consumption and moderate linearity. Instead of simply using standard Gilbert cell and focus on its optimization, as it is quite often done in the literature, three mixer topologies, are examined. The evaluation is done analytically and by simulations with SpectreRF. A novel folded switching mixer topology achieves the best performance. With this topology the following simulation results are achieved: noise figure (NF) 14 dB, voltage gain (G) 17 dB, linearity (IIP3) 1 dBm with a power consumption of 4 5 mW at the operating frequency of 2 5 GHz. Good matching between expected and simulated results is observed. A low voltage operation, which implies robustness for technology scaling, is also considered. At the end the final results are reported and the most promising topology is selected. Keywords— Multi-Standard Receiver, CMOS Mixer, Low voltage operation